1. Field of the Invention
The present invention relates to a semiconductor integrated circuit system, a semiconductor integrated circuit and a method for driving a semiconductor integrated circuit system. More particularly, the present invention relates to a semiconductor integrated circuit system for high-speed data transfer in synchronization with a clock, a method for driving such a semiconductor integrated circuit system, and a semiconductor integrated circuit for use in such a semiconductor integrated circuit system.
2. Description of the Related Art
In recent years, a new line of products has been developed for use in multimedia applications. One major feature of a multimedia application is the capability of handling motion pictures as well as characters, still images and sounds. Motion picture processing involves a huge amount of data, thereby requiring a high data transfer rate. One way to realize such a high data transfer rate is to increase a bus width of a data bus so as to transfer a large amount of data. However, when the bus width of a data bus is increased, the scale of the system is adversely increased. In view of this, it has been proposed to increase the data transfer rate (clock frequency) without increasing the bus width of a data bus so as to provide a semiconductor integrated circuit system capable of transferring a large amount of data at a very high speed.
For example, a system using SyncLink DRAM, which inputs/outputs data at the dual edges of the clock, has been proposed and is described in Draft Standard for A High-Speed Memory Interface (SyncLink)-Draft 0.99 IEEE P1596.7-199X or xe2x80x9cRAMBUS; PRODUCT CATALOGxe2x80x9d. In such a semiconductor integrated circuit system, when the clock speed is increased in order to realize a high-speed data transfer, problems occur such as a clock skew or a skew between chips, due to the difference between the distance (bus length) from one slave chip to the master chip and the distance from another slave chip to the master chip. In view of this, in the above-described SyncLink system, the slave chips are each provided with a circuit for delaying (or adjusting the phase of) the data output clock for controlling the timing of data output based on the positional relationship with (or the bus length to) the master chip, as illustrated in Draft 0.99 IEEE P1596.7-199X, P.43, FIG. 36, for example.
The distance from each slave chip to the master chip is detected at initialization of the system, so that a predetermined amount of delay in accordance with the distance is set in a circuit for adjusting the phase of the clock (hereinafter, referred to simply as the xe2x80x9cclock phase adjustment circuitxe2x80x9d) in the slave chip. The phase of the data output clock of each slave chip is adjusted as described above, so that the master chip can receive data from respective slave chips simultaneously, whereby it is possible to stably perform high-speed data transfer.
However, such a conventional integrated circuit system as described above may include IC chips (semiconductor integrated circuits) which are not all from the same manufacturer. Among IC chips from different manufacturers, dependency or source voltage dependency) of the data output clock phase adjustment circuit provided in one IC chip may differ from those of another IC chip. The inventors of the present invention found that such difference in the characteristics of the data output clock phase adjustment circuit among the IC chips is particularly problematic in systems for high-speed data transfer such as those operating at a clock frequency of 200 MHz or higher. Such a change in the temperature or source voltage in a semiconductor integrated circuit system can easily occur, for example, due to the increasing temperature during use or when running an application with a large power consumption.
Thus, when a semiconductor integrated circuit system has IC chips from various manufacturers, even if a proper amount of delay is set, at system initialization, for the clock phase adjustment circuit of each IC chip in accordance with the bus length thereof, when an operating condition of the system such as the temperature or source voltage thereof changes from that at initialization, the amount of delay of each IC chip shifts from the proper value. Since the shift in the amount of delay may vary among the IC chips depending upon the characteristics (e.g., the temperature dependency, the voltage dependency, etc.) of the clock phase adjustment circuits of the respective IC chips, the amount of delay of each IC chip gradually becomes mismatched with another as the operation conditions of the system change. Then, the clock skew among the IC chips cannot be compensated for, whereby the stable operation of the system may not be ensured.
Moreover, even if the manufacturers make an agreement on standardizing those characteristics such as the temperature dependency or voltage dependency of a transistor, for example, it is difficult for the manufacturers to standardize such device characteristics over a wide range of temperature or voltage (e.g., to standardize the temperature dependency over a range of xe2x88x92100xc2x0 C. to +100xc2x0 C.). Therefore, such an agreement is not realistic.
Furthermore, even when the system is provided with IC chips from one manufacturer, the IC chips do not always have the same circuit characteristics due to possible variation among different lots.
According to one aspect of this invention, a semiconductor integrated circuit system, having one master chip and a plurality of slave chips, for performing data transfer under a control of a predetermined clock is provided. The system includes: a detection section for detecting a change in a state of the semiconductor integrated circuit system and for producing information indicating the detection result, the state including at least one of temperature and source voltage; and at least one clock phase adjustment section for receiving the information and for adjusting a phase of a clock used in transferring data output by the slave chip based on the information.
In one embodiment of the invention, the detection section is controlled by the master chip, and the at least one clock phase adjustment section is included in the slave chip.
In one embodiment of the invention, the master chip and the plurality of slave chips are each connected to a command bus for transferring a command, a first clock line carrying a command clock for controlling the command transfer, a data bus for transferring data and a second clock line carrying a data clock for controlling the data transfer. The detection section is provided in the master chip. The master chip further includes: a command production section for producing a command including as a part thereof the information produced by the detection section; and a command output section for outputting the command to the command bus based on the command clock. The slave chip includes: a clock input section for receiving the command clock from the first clock line; an input section for receiving the command from the command bus in accordance with the command clock; an extraction section for extracting the information included in the received command; a data output section for outputting data in the slave chip to the data bus in accordance with the data clock; and a clock output section for outputting the data clock to the second clock line. The at least one clock phase adjustment section receives the command clock and produces a data clock by adjusting a phase of the command clock based on the change in the state of the semiconductor integrated circuit system indicated by the information extracted by the extraction section.
In one embodiment of the invention, the command is transferred in a packet; and the command production section produces a command packet including the information and a chip ID.
In one embodiment of the invention, the at least one clock phase adjustment section comprises a plurality of delay units which are selectively used based on the change in the state of the semiconductor integrated circuit system.
In one embodiment of the invention, each of the plurality of slave chips comprises the detection section and the at least one clock phase adjustment section.
In one embodiment of the invention, the master chip and the plurality of slave chips are each connected to a command bus for transferring a command, a first clock line carrying a command clock for controlling the command transfer, a data bus for transferring data and a second clock line carrying a data clock for controlling the data transfer. Each of the plurality of slave chips further includes: a clock input section for receiving the command clock from the first clock line; an input section for receiving the command from the command bus in accordance with the command clock; a data output section for outputting data in the slave chip obtained based on the received command to the data bus in accordance with the data clock; and a clock output section for outputting the data clock to the second clock line. The at least one clock phase adjustment section produces the data clock by adjusting a phase of the command clock based on the change in the state of the semiconductor integrated circuit system indicated by the information provided by the detection section.
In one embodiment of the invention, the at least one clock phase adjustment section includes first and second clock phase adjustment sections. While one of the first clock phase adjustment section and the second clock phase adjustment section is performing phase adjustment in one operating cycle, the other one prepares for phase adjustment in a next operating cycle.
According to another aspect of this invention, a semiconductor integrated circuit operating in synchronization with a predetermined clock is provided. The semiconductor integrated circuit includes: a clock input section for receiving a command clock; a command input section for receiving a command in accordance with the command clock, the command including information indicating a change in a state which includes at least one of temperature and source voltage; an extraction section for extracting the information from the received command; at least one clock phase adjustment section for producing a data clock by adjusting a phase of the received command clock based on the change in the state indicated by the information extracted by the extraction section; a data output section for outputting data in the slave chip in accordance with the data clock; and a clock output section for outputting the data clock.
In one embodiment of the invention, the at least one clock phase adjustment section includes first and second clock phase adjustment sections. While one of the first clock phase adjustment section and the second clock phase adjustment section is performing phase adjustment in one operating cycle, the other one prepares for phase adjustment in a next operating cycle.
According to still another aspect of this invention, a semiconductor integrated circuit operating in synchronization with a predetermined clock is provided. The semiconductor integrated circuit includes: a clock input section for inputting a reference clock; a synchronization section for producing an internal clock corresponding to a source voltage level, the synchronization section receiving the reference clock, outputting the internal clock in synchronization with the reference clock by changing the source voltage level, and outputting as a reference voltage signal a source voltage level which is determined by synchronizing the internal clock with the reference clock; a source voltage generation section for generating a supply voltage based on the reference voltage signal; a clock phase adjustment section for receiving the internal clock, and outputting an output control clock by adjusting a phase of the internal clock based on the source voltage; and a data output section for outputting data in the semiconductor integrated circuit in accordance with the output control clock.
In one embodiment of the invention, a frequency of the reference clock in an operating mode of the semiconductor integrated circuit is different from that in a stand-by mode of the semiconductor integrated circuit system.
In one embodiment of the invention, the frequency of the reference clock in the operating mode is greater than that in the stand-by mode.
In one embodiment of the invention, the source voltage generation section includes a first source voltage generation section used in an operating mode of the semiconductor integrated circuit and a second source voltage generation section used in a stand-by mode of the semiconductor integrated circuit.
According to still another aspect of this invention, a semiconductor integrated circuit operating in synchronization with a predetermined clock is provided. The semiconductor integrated circuit includes: a first clock input section for inputting a reference clock; a second clock input section for inputting an adjustment clock; a synchronization section for producing an internal clock corresponding to a source voltage level, the synchronization section receiving the adjustment clock, synchronizing the internal clock with the adjustment clock by changing the source voltage level, and outputting as a reference voltage signal a source voltage level which is determined by the synchronization; a source voltage generation section for generating a source voltage based on the reference voltage signal; a clock phase adjustment section for receiving the reference clock, and outputting an output control clock by adjusting a phase of the reference clock based on the source voltage; and a data output section for outputting data in the semiconductor integrated circuit in accordance with the output control clock.
In one embodiment of the invention, the second clock input section produces the adjustment clock by dividing a frequency of the reference clock from the first clock input section.
According to still another aspect of this invention, a method for driving a semiconductor integrated circuit system which has one master chip and a plurality of slave chips for performing data transfer under a control of a predetermined clock is provided. The method includes the steps of: initializing a data transfer clock in each slave chip after power-up and before starting a read/write operation: detecting changes in temperature and source voltage so as to produce an information signal indicating the detection result; and adjusting a phase of the initialized data transfer clock in each slave chip based on the information signal.
Thus, the invention described herein makes possible the advantages of: (1) providing a semiconductor integrated circuit system capable of stably operating at a high speed even when a semiconductor integrated circuit system has IC chips from various manufacturers, or when the circuit characteristics (e.g., the temperature dependency, the voltage dependency, etc.) vary among respective IC chips; (2) providing a semiconductor integrated circuit for use in such a semiconductor integrated circuit system; and (3) providing a method for driving such a semiconductor integrated circuit system.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.